1. Field of the Invention
The present invention relates to a semiconductor memory device, such as a static RAM or the like, which has a function of testing a read operation for screening.
2. Description of the Background Art
In recent years, the integration degree of transistors formed in a semiconductor integrated circuit is more and more increased with the advance of technology. Also, the memory size of an SRAM or the like which is essentially required for constituting a system circuit on a chip ever increases, and thus, the area of a memory region on a chip also tends to increase. In general semiconductor memory devices, the area of the memory region is scaled down by reducing the transistor size of each memory cell to the extent possible so as to suppress a decrease in yield and an increase in chip cost due to an increase in the area of the memory region.
When the transistor size is decreased, the driving capacity of the transistor in a memory cell is reduced, resulting in a slow read speed. To solve the problem, a technique of amplifying data retrieved from the memory cell by a sense amplifier has been conventionally used to improve a read speed.
However, memories with such a structure are likely to have a poorly-reproducible defect, since an operation of reading and amplifying minute data is easily affected by external disturbance. For example, a read operation may be performed normally or erroneously, depending on an operating condition during the read operation. As the area of the memory region is increased, a probability that dust enters the memory region during a manufacturing process increases, leading to an increase in rate of memories having a poor-reproducibile defect. An integrated circuit device having such a memory which has a poor-reproducible defect, which may be recognized as a non-defective product during a test operation, is likely to malfunction and cause an enormous trouble in an electronic apparatus in which the integrated circuit device is incorporated. Therefore, it is necessary to reliably screen out a memory which has a poor-reproducibile defect, during the test operation.
Conventionally, a test method of detecting not only a memory which has a easily detectable defect, but also a memory which has a poor-reproducibile defect, has been conventionally proposed (see, for example, Japanese Patent Laid-Open Publication No. 02-206087). Here, the conventional defect detecting method will be described with reference to FIGS. 12 and 13. FIG. 12 illustrates a circuit configuration of a semiconductor memory device having a static RAM. The semiconductor memory device is composed of memory cells Mn_m (n: 1, 2, 3, . . . ; m: 1, 2, 3, . . . ) which are arranged in a matrix within a memory region, and a peripheral circuit.
Each memory cell Mn_m is composed of two inverter circuits 21a and 21b which constitute a latch for holding data, and access transistors 22a and 22b which connect the latch and bit lines BLm and NBLm (m: 1, 2, 3, . . . ) and whose gate electrodes are connected to a word line WLn. For example, each memory cell Mn_m stores “1” when left and right memory holding nodes (latch nodes) have an H level and an L level, respectively, as in a memory cell M1_1 of FIG. 12, and stores “0” when the left and right memory holding nodes have the L level and the H level, respectively, as in the memory cell M2_1.
A read operation of the SRAM circuit of FIG. 12 will be described with reference to a timing chart of FIG. 13. In the timing chart, a time period T1 indicates an ordinary read operation (ordinary mode) period, and a time period T2 indicates a test operation (test mode) period. In an initial state, each pair of bit lines BLm and NBLm are precharged to an H level corresponding to a power supply voltage (VDD). For example, when a stored value is read out from the memory cell M1_1 and when the memory cell M1_is tested, the memory holding nodes of the memory cell M1_m and the pair of bit lines BLm and NBLm are brought into conduction by causing the potential level of the word line WL1 to rise to the H level. Thereby, the potential of the bit line BLm or NBLm gradually falls to the L level, so that a potential difference occurs between the pair of bit lines BLm and NBLm.
Here, it is assumed that the access transistor 22b of the memory cell M1_1 has a defect, and therefore, has lower driving capacity than that of the normal access transistor 22b of the memory cell M1_2. Therefore, a potential falling rate of the bit line NBL1 is slower than that of the bit line BL2.
A select circuit 35 outputs a signal obtained by delaying a pulse signal SA using a delay circuit 36, as a sense amplifier activating signal SAE, during the ordinary read operation, and outputs the pulse signal SA without a delay in the delay circuit 36, as a sense amplifier activating signal SAE, during the test operation. A sense amplifier 32, when receiving the sense amplifier activating signal SAE, amplifies a differential input of the pair of bit lines BL1 and NBL1 selected by a column selector 31, and outputs the result as a sense output SO. Note that it is determined on the basis of a test mode signal TST whether or not the signal SA is delayed by the delay circuit 36.
During the ordinary read operation, the potential difference between the pair of bit lines BL1 and NBL1 when the defective memory cell M1_is read may become equal to a threshold potential difference (offset voltage) required for a correct operation of the sense amplifier 32, depending on a time until the sense amplifier 32 is activated. In this case, the sense amplifier output SO is likely to become unstable, i.e., go to the H level (normal read operation) at some times or the L level (erroneous read operation) at other times.
On the other hand, during the test operation, sense amplifier activation timing is earlier than that during the ordinary read operation, and therefore, a variation in the potential difference of the pair of bit lines BL1 and NBL1 is smaller than that during the ordinary read operation. Thus, conventionally, a test method of determining a stored value using a smaller potential difference between a pair of bit lines by setting the timing of activating the sense amplifier 32 to be earlier than that during the ordinary read operation, has been proposed.
However, in the conventional technique, a difference between a read potential during the ordinary read operation and a read potential during the test operation is determined by a cell current when the sense amplifier is activated, and has a value in proportional to the cell current. Therefore, a difference between a cell current during the ordinary read operation and a cell current during the test operation, which is set under an assumption that external disturbance noise occurs, depends on the driving capacity of each memory cell, and varies among memory cells. When a memory cell having an extremely small cell current is tested, a sufficient test margin cannot be obtained, so that an unstable defect may not be detected.
In the read technique of amplifying a minute potential difference, it is determined whether or not a test is normally performed, depending on a relationship between the magnitude of a threshold potential difference (offset voltage) for correctly operating a sense amplifier, and the driving capacity of the memory cell Mn_m which causes the potential difference. The above-described conventional technique is effective when the offset voltage is increased due to a variation in characteristics of a transistor included in the sense amplifier 32 and therefore an unstable state occurs. However, the above-described conventional technique is not very effective when there is substantially no offset voltage and the cell current is small, nevertheless an unstable state occurs. To detect the latter defect which causes an unstable state, it is necessary to advance the activation timing of the sense amplifier to a large extent. In this case, however, a memory cell, which operates stably and normally, is likely to be read in an abnormal manner, resulting in an adverse effect, such as a reduction in yield.